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C= commodore 64

Commodore 128 Input/Output Assignments

; Commodore 128 I/O Map ; V1.2 22 Jun 1994 COMMODORE 128 INPUT/OUTPUT ASSIGNMENTS Differences Between C64 and C128 D500-D50B MMU D600-D601 VDC FF00-FF05 Preconfiguration Registers HEX DECIMAL BITS DESCRIPTION 8502 I/O Registers C128 mode: 0000 x 0 1 0 1 1 1 1 0001 x Caps Motor Sense Write HIRAM LORAM CHAREN C64 mode: 0000 0 6-0 MOS 8502 Data Direction Register (xx101111) Bit= 1: Output, Bit=0: Input, x=Don't Care 0001 1 MOS 8502 Micro-Processor On-Chip I/O Port 0 /LORAM Signal (0=Switch BASIC ROM Out) 1 /HIRAM Signal (0=Switch Kernal ROM Out) 2 /CHAREN Signal (O=Swith Char. ROM In) 3 Cassette Data Output Line 4 Cassette Switch Sense: 1 = Switch Closed 5 Cassette Motor Control O = ON, 1 = OFF 6 Caps Lock (ASCII/CC, ASCII/DIN) key D000-D02E 53248-54271 MOS 6566 VIDEO INTERFACE CONTROLLER (VIC) D000 53248 Sprite O X Pos D001 53249 Sprite O Y Pos D002 53250 Sprite 1 X Pos D003 53251 Sprite 1 Y Pos D004 53252 Sprite 2 X Pos D005 53253 Sprite 2 Y Pos D006 53254 Sprite 3 X Pos D007 53255 Sprite 3 Y Pos D008 53256 Sprite 4 X Pos D009 53257 Sprite 4 Y Pos D00A 53258 Sprite 5 X Pos D00B 53259 Sprite 5 Y Pos D00C 53260 Sprite 6 X Pos D00D 53261 Sprite 6 Y Pos D00E 53262 Sprite 7 X Pos D00F 53263 Sprite 7 Y Pos D010 53264 Sprites 0-7 X Pos (msb of X coord.) D011 53265 VIC Control Register 7 Raster Compare: (Bit 8) See 53266 6 Extended Color Text Mode 1 = Enable 5 Bit Map Mode. 1 = Enable 4 Blank Screen to Border Color: O = Blank 3 Select 24/25 Row Text Display: 1 = 25 Rows 2-0 Smooth Scroll to Y Dot-Position (0-7) D012 53266 Read Raster / Write Raster Value for Compare IRQ D013 53267 Light-Pen Latch X Pos D014 53268 Light-Pen Latch Y Pos D015 53269 Sprite display Enable: 1 = Enable D016 53270 VIC Control Register 7-6 Unused 5 ALWAYS SET THIS BIT TO 0 ! 4 Multi-Color Mode: 1 = Enable (Text or Bit-Map) 3 Select 38/40 Column Text Display: 1 = 40 Cols 2-0 Smooth Scroll to X Pos D017 53271 Sprites O-7 Expand 2x Vertical (Y) D018 53272 VIC Memory Control Register 7-4 Video Matrix Base Address (inside VIC) 3-1 Character Dot-Data Base Address (inside VIC) 0 Select upper/lower Character Set D019 53273 VIC Interrupt Flag Register (Bit = 1: IRQ Occurred) 7 Set on Any Enabled VIC IRQ Condition 3 Light-Pen Triggered IRQ Flag 2 Sprite to Sprite Collision IRQ Flag 1 Sprite to Background Collision IRQ Flag 0 Raster Compare IRQ Flag D01A 53274 IRQ Mask Register: 1 = Interrupt Enabled D01B 53275 Sprite to Background Display Priority: 1 = Sprite D01C 53276 Sprites O-7 Multi-Color Mode Select: 1 = M.C.M. D01D 53277 Sprites 0-7 Expand 2x Horizontal (X) D01E 53278 Sprite to Sprite Collision Detect D01F 53279 Sprite to Background Collision Detect D020 53280 Border Color D021 53281 Background Color O D022 53282 Background Color 1 D023 53283 Background Color 2 D024 53284 Background Color 3 D025 53285 Sprite Multi-Color Register 0 D026 53286 Sprite Multi-Color Register 1 D027 53287 Sprite O Color D028 53288 Sprite 1 Color D029 53289 Sprite 2 Color D02A 53290 Sprite 3 Color D02B 53291 Sprite 4 Color D02C 53292 Sprite 5 Color D02D 53293 Sprite 6 Color D02E 53294 Sprite 7 Color D02F 53295 7-3 Unused 2-0 Additional Keyboard Columns D030 53296 7-2 Unused 1 Test 0 2 MHz Mode D400-D4FF 54272-52527 MOS 6581 SOUND INTERFACE DEVICE (SID) D400 54272 Voice 1: Frequency Control - Low-Byte D401 54273 Voice 1: Frequency Control - High-Byte D402 54274 Voice 1: Pulse Waveform Width - Low-Byte D403 54275 7-4 Unused 3-0 Voice 1: Pulse Waveform Width - High-Nybble D404 54276 Voice 1: Control Register 7 Select Random Noise Waveform, 1 = On 6 Select Pulse Waveform, 1 = On 5 Select Sawtooth Waveform, 1 = On 4 Select Triangle Waveform, 1 = On 3 Test Bit: 1 = Disable Oscillator 1 2 Ring Modulate Osc. 1 with Osc. 3 Output, 1 = On 1 Synchronize Osc. 1 with Osc. 3 Frequency, 1 = On 0 Gate Bit: 1 = Start Att/Dec/Sus, 0 = Start Release D405 54277 Envelope Generator 1: Attack / Decay Cycle Control 7-4 Select Attack Cycle Duration: O-15 3-0 Select Decay Cycle Duration: 0-15 D406 54278 Envelope Generator 1: Sustain / Release Cycle Control 7-4 Select Sustain Cycle Duration: O-15 3-0 Select Release Cycle Duration: O-15 D407 54279 Voice 2: Frequency Control - Low-Byte D408 54280 Voice 2: Frequency Control - High-Byte D409 54281 Voice 2: Pulse Waveform Width - Low-Byte D40A 54282 7-4 Unused 3-0 Voice 2: Pulse Waveform Width - High-Nybble D40B 54283 Voice 2: Control Register 7 Select Random Noise Waveform, 1 = On 6 Select Pulse Waveform, 1 = On 5 Select Sawtooth Waveform, 1 = On 4 Select Triangle Waveform, 1 = On 3 Test Bit: 1 = Disable Oscillator 1 2 Ring Modulate Osc. 2 with Osc. 1 Output, 1 = On 1 Synchronize Osc. 2 with Osc. 1 Frequency, 1 = On 0 Gate Bit: 1 = Start Att/Dec/Sus, 0 = Start Release D40C 54284 Envelope Generator 2: Attack / Decay Cycle Control 7-4 Select Attack Cycle Duration: O-15 3-0 Select Decay Cycle Duration: 0-15 D40D 54285 Envelope Generator 2: Sustain / Release Cycle Control 7-4 Select Sustain Cycle Duration: O-15 3-0 Select Release Cycle Duration: O-15 D40E 54286 Voice 3: Frequency Control - Low-Byte D40F 54287 Voice 3: Frequency Control - High-Byte D410 54288 Voice 3: Pulse Waveform Width - Low-Byte D411 54289 7-4 Unused 3-0 Voice 3: Pulse Waveform Width - High-Nybble D412 54290 Voice 3: Control Register 7 Select Random Noise Waveform, 1 = On 6 Select Pulse Waveform, 1 = On 5 Select Sawtooth Waveform, 1 = On 4 Select Triangle Waveform, 1 = On 3 Test Bit: 1 = Disable Oscillator 1 2 Ring Modulate Osc. 3 with Osc. 2 Output, 1 = On 1 Synchronize Osc. 3 with Osc. 2 Frequency, 1 = On 0 Gate Bit: 1 = Start Att/Dec/Sus, 0 = Start Release D413 54291 Envelope Generator 3: Attac/Decay Cycle Control 7-4 Select Attack Cycle Duration: O-15 3-0 Select Decay Cycle Duration: 0-15 D414 54285 Envelope Generator 3: Sustain / Release Cycle Control 7-4 Select Sustain Cycle Duration: O-15 3-0 Select Release Cycle Duration: O-15 D415 54293 Filter Cutoff Frequency: Low-Nybble (Bits 2-O) D416 54294 Filter Cutoff Frequency: High-Byte D417 54295 Filter Resonance Control / Voice Input Control 7-4 Select Filter Resonance: 0-15 3 Filter External Input: 1 = Yes, 0 = No 2 Filter Voice 3 Output: 1 = Yes, 0 = No Filter Voice 2 Output: 1 = Yes, 0 = No 0 Filter Voice 1 Output: 1 = Yes, 0 = No D418 54296 Select Filter Mode and Volume 7 Cut-Off Voice 3 Output: 1 = Off, O = On 6 Select Filter High-Pass Mode: 1 = On 5 Select Filter Band-Pass Mode: 1 = On 4 Select Filter Low-Pass Mode: 1 = On 3-0 Select Output Volume: 0-15 D419 54297 Analog/Digital Converter: Game Paddle 1 (O-255) D41A 54298 Analog/Digital Converter Game Paddle 2 (O-255) D41B 54299 Oscillator 3 Random Number Generator D41C 54230 Envelope Generator 3 Output MMU $D500 and $FF00 C128 MMU 8722 D500 Configuration Register (CR) 7-6 RAM-select 0-3 5-4 High RAM/ROM 00 System ROM (Kernel, Edit) 01 Internal Function ROM 10 External Function ROM 11 RAM NOTE: I/O overrides all of these. 3-2 Mid RAM/ROM 00 System ROM (Basic HI) 01 Internal Function ROM 10 External Function ROM 11 RAM 1 Lo RAM 0 System ROM (Basic LO) 1 RAM 0 C.GEN 0 I/O 1 ROM/RAM D501 Preconfiguration Registers D502 D503 D504 D505 7 40/80 read only 6 C64 Mode (0 = C128) 5 EXROM: C64 (1 = C128) read only 4 GAME: C64 (1 = C128) read only 3 FSDIR: Fast Disk Transfer Direction 2-1 - 0 Z80/8502 D506 RAM Configuration Register (RCR) 7-6 Video-Bank 5-4 - 3 Shared RAM Hi 2 Shared RAM Lo 1-0 Shared RAM Size: 00 = 1K, 01 = 4K, 10 = 8K, 11 = 16K D507 Zero Page Pointer Lo 7-0 A15-A8 D508 Zero Page Pointer Hi 7-4 - 3-2 A19-A18 (Used in 1MB System) 1-0 A17-A16 (256K System) D509 Stack Page Pointer Lo D50A Stack Page Pointer Hi D50B MMU Version Register 7-4 Bank Version (2 = 128K) 3-0 MMU Version Default Memory Configurations Bank FF00 Free RAM Space RAM I/O ROM 0 3f 0000-ffff 0 1 7f 0000-ffff 1 2 bf 0000-ffff 2 3 ff 0000-ffff 3 4 16 0000-7fff 0 I/O Int 5 56 0000-7fff 1 I/O Int 6 96 0000-7fff 2 I/O Int 7 d6 0000-7fff 3 I/O Int 8 2a 0000-7fff 0 I/O Ext 9 6a 0000-7fff 1 I/O Ext 10 aa 0000-7fff 2 I/O Ext 11 ea 0000-7fff 3 I/O Ext 12 06 0000-7fff 0 I/O Kernel Int_Rom_Low 13 0a 0000-7fff 0 I/O Kernel Ext_Rom_Low 14 01 0000-3fff 0 Char Kernel Basic 15 00 0000-3fff 0 I/O Kernel Basic VDC $D600 This register map is from C-Hacking Magazine. ---------------------------------- | VDC 8563 Register Definitions | ---------------------------------- Reg 7 6 5 4 3 2 1 0 Description Notes ------ ---- ---- ---- ---- ---- ---- ---- ---- ------------------------ ----- 0 HzT7 HzT6 HzT5 HzT4 HzT3 HzT2 HzT1 HzT0 Horizontal Total ^1 1 HzD7 HzD6 HzD5 HzD4 HzD3 HzD2 HzD1 HzD0 Horizontal Displayed ^1 2 HzS7 HzS6 HzS5 HzS4 HzS3 HzS2 HzS2 HzS0 Horizontal Sync Position ^1 3 VSW3 VSW2 VSW1 VSW0 HSW3 HSW2 HSW1 HSW0 Vert/Horiz. Sync Width ^2 4 VeT7 VeT6 VeT5 VeT4 VeT3 VeT2 VeT1 VeT0 Vertical Total ^3 5 .... .... .... VeA4 VeA3 VeA2 VeA1 VeA0 Vertical Total Fine Adju ^3 6 VeD7 VeD6 VeD5 VeD4 VeD3 VeD2 VeD1 VeD0 Vertical Displayed ^3 7 VeS7 VeS6 VeS5 VeS4 VeS3 VeS2 VeS1 VeS0 Vertical Sync Position ^2 8 .... .... .... .... .... .... Ilc1 Ilc0 Interlace Mode ^4 9 .... .... .... CTV4 CTV3 CTV2 CTV1 CTV0 Character Total Vertical ^5 0a 10 .... CrM1 CrM0 Css4 Css3 Css2 Css1 Css0 Cursor Mode/ Start Scan ^6 0b 11 .... .... .... Ces4 Ces3 Ces2 Ces1 Ces0 Cursor End Scan ^6 0c 12 Ds15 Ds14 Ds13 Ds12 Ds11 Ds10 Ds09 Ds08 Display Start Adrs (Hi) ^7 0d 13 Ds07 Ds06 Ds05 Ds04 Ds03 Ds02 Ds01 Ds00 Display Start Adrs (Lo) ^7 0e 14 Cp15 Cp14 Cp13 Cp12 Cp11 Cp10 Cp09 Cp08 Cursor Position (Hi) ^7 0f 15 Cp07 Cp06 Cp05 Cp04 Cp03 Cp02 Cp01 Cp00 Cursor Position (Lo) ^7 10 16 LpV7 LpV6 LpV5 LpV4 LpV3 LpV2 LpV1 LpV0 Light Pen Veritcal ^8 11 17 LpH7 LpH6 LpH5 LpH4 LpH3 LpH2 LpH1 LpH0 Light Pen Horizontal ^8 12 18 Ua15 Ua14 Ua13 Ua12 Ua11 Ua10 Ua09 Ua08 Update Address (Hi) ^9 13 19 Ua07 Ua06 Ua05 Ua04 Ua03 Ua02 Ua01 Ua00 Update Address (Lo) ^9 14 20 At15 At14 At13 At12 At11 At10 At09 At08 Attribute Start Adrs (Hi) ^7 15 21 At07 At06 At05 At04 At03 At02 At01 At00 Attribute Start Adrs (Lo) ^7 16 22 HcP3 HcP2 HcP1 HcP0 IcS3 IcS2 IcS1 IcS0 Hz Chr Pxl Ttl/IChar Spc ^A 17 23 .... .... .... VcP4 VcP3 VcP2 VcP1 VcP0 Vert. Character Pxl Spc ^5 18 24 BlkM RvsS Vss5 Vss4 Vss3 Vss2 Vss1 Vss0 Block/Rvs Scr/V. Scroll ^9^B^C 19 25 Text Atri Semi Dble Hss3 Hss2 Hss1 Hss0 Diff. Mode Sw/H. Scroll ^D,^E 1a 26 Fgd3 Fgd2 Fgd1 Fgd0 Bgd3 Bgd2 Bgd1 Bgd0 ForeGround/BackGround Col ^F 1b 27 Rin7 Rin6 Rin5 Rin4 Rin3 Rin2 Rin1 Rin0 Row/Adrs. Increment ^G 1c 28 CSa2 CSa1 CSa0 RamT .... .... .... .... Character Set Addrs/Ram ^H,^I 1d 29 .... .... .... UdL4 UdL3 UdL2 UdL1 UdL0 Underline Scan Line ^6 1e 30 WdC7 WdC6 WdC5 WdC4 WdC3 WdC2 WdC1 WdC0 Word Count (-1) ^9 1f 31 Dta7 Dta6 Dta5 Dta4 Dta3 Dta2 Dta1 Dta0 Data ^9 20 32 BlkF BlkE BlkD BlkC BlkB BlkA Blk9 Blk8 Block Copy Source (hi) ^9 21 33 Blk7 Blk6 Blk5 Blk4 Blk3 Blk2 Blk1 Blk0 Block Copy Source (lo) ^9 22 34 DeB7 DeB6 DeB5 DeB4 DeB3 DeB2 DeB1 DeB0 Display Enable Begin ^J 23 35 DeE7 DeE6 DeE5 DeE4 DeE3 DeE2 DeE1 DeE0 Display Enable End ^J 24 36 .... .... .... .... Drm3 Drm2 Drm1 Drm0 DRAM Refresh Rate ^K D800-DBFF 55296-56319 Color RAM (Nybbles) DC00-DCFF 56320-56575 MOS 6526 Complex Interface Adapter (CIA) #1 DC00 56320 Data Port A (Keyboard, Joystick, Paddles, Light-Pen) 7-0 Write Keyboard Column Values for Keyboard Scan 7-6 Read Paddles on Port A / B (01 = Port A, 10 = Port B) 4 Joystick A Fire Button: 1 = Fire 3-2 Paddle Fire Buttons 3-0 Joystick A Direction (0-15) DC01 56321 Data Port B (Keyboard, Joystick, Paddles): Game Port 1 7-0 Read Keyboard Row Values for Keyboard Scan 7 Timer B Toggle/Pulse Output 6 Timer A: Toggle/Pulse Output 4 Joystick 1 Fire Button: 1 = Fire 3-2 Paddle Fire Buttons 3-0 Joystick 1 Direction DC02 56322 Data Direction Register - Port A (56320) DC03 56323 Data Direction Register - Port B (56321) DC04 56324 Timer A: Low-Byte DC05 56325 Timer A: High-Byte DC06 56326 Timer B: Low-Byte DC07 56327 Timer B: High-Byte DC08 56328 Time-of-Day Clock: 1/10 Seconds DC09 56329 Time-of-Day Clock: Seconds DC0A 56330 Time-of-Day Clock: Minutes DC0B 56331 Time-of-Day Clock: Hours + AM/PM Flag (Bit 7) DC0C 56332 Synchronous Serial I/O Data Buffer DC0D 56333 CIA Interrupt Control Register (Read IRQs/Write Mask) 7 IRQ Flag (1 = IRQ Occurred) / Set-Clear Flag 4 FLAG1 IRQ (Cassette Read / Serial Bus SRQ Input) 3 Serial Port Interrupt 2 Time-of-Day Clock Alarm Interrupt 1 Timer B Interrupt 0 Timer A Interrupt DC0E 56334 CIA Control Register A 7 Time-of-Day Clock Frequency: 1 = 50 Hz, 0 = 60 Hz 6 Serial Port I/O Mode Output, 0 = Input 5 Timer A Counts: 1 = CNT Signals, 0 = System 02 Clock 4 Force Load Timer A: 1 = Yes 3 Timer A Run Mode: 1 = One-Shot, 0 = Continuous 2 Timer A Output Mode to PB6: 1 = Toggle, 0 = Pulse 1 Timer A Output on PB6: 1 = Yes, 0 = No 0 Start/Stop Timer A: 1 = Start, 0 = Stop DC0F 56335 CIA Control Register B 7 Set Alarm/TOD-Clock: 1 = Alarm, 0 = Clock 6-5 Timer B Mode Select: 00 = Count System 02 Clock Pulses 01 = Count Positive CNT Transitions 10 = Count Timer A Underflow Pulses 11 = Count Timer A Underflows While CNT Positive 4-0 Same as CIA Control Reg. A - for Timer B DD00-DDFF 56576-56831 MOS 6526 Complex Interface Adapter (CIA) #2 DD00 56576 Data Port A (Serial Bus, RS-232, VIC Memory Control) 7 Serial Bus Data Input 6 Serial Bus Clock Pulse Input 5 Serial Bus Data Output 4 Serial Bus Clock Pulse Output 3 Serial Bus ATN Signal Output 2 RS-232 Data Output (User Port) 1-O VIC Chip System Memory Bank Select (Default = 11) DD01 56577 Data Port B (User Port, RS-232) 7 User / RS-232 Data Set Ready 6 User / RS-232 Clear to Send 5 User 4 User / RS-232 Carrier Detect 3 User / RS-232 Ring Indicator 2 User / RS-232 Data Terminal Ready 1 User / RS-232 Request to Send 0 User / RS-232 Received Data DD02 56578 Data Direction Register - Port A DD03 56579 Data Direction Register - Port B DD04 56580 Timer A: Low-Byte DD05 56581 Timer A: High-Byte DD06 56582 Timer B: Low-Byte DD07 56583 Timer B: High-Byte DD08 56584 Time-of-Day Clock: 1/10 Seconds DD09 56585 Time-of-Day Clock: Seconds DD0A 56586 Time-of-Day Clock: Minutes DD0B 56587 Time-of-Day Clock: Hours + AM/PM Flag (Bit 7) DD0C 56588 Synchronous Serial I/O Data Buffer DD0D 56589 CIA Interrupt Control Register (Read NMls/Write Mask) 7 NMI Flag (1 = NMI Occurred) / Set-Clear Flag 4 FLAG1 NMI (User/RS-232 Received Data Input) 3 Serial Port Interrupt 1 Timer B Interrupt 0 Timer A Interrupt DD0E 56590 CIA Control Register A 7 Time-of-Day Clock Frequency: 1 = 50 Hz, 0 = 60 Hz 6 Serial Port I/O Mode Output, 0 = Input 5 Timer A Counts: 1 = CNT Signals, 0 = System 02 Clock 4 Force Load Timer A: 1 = Yes 3 Timer A Run Mode: 1 = One-Shot, 0 = Continuous 2 Timer A Output Mode to PB6: 1 = Toggle, 0 = Pulse 1 Timer A Output on PB6: 1 = Yes, 0 = No 0 Start/Stop Timer A: 1 = Start, 0 = Stop DD0F 56591 CIA Control Register B 7 Set Alarm/TOD-Clock: 1 = Alarm, 0 = Clock 6-5 Timer B Mode Select: 00 = Count System 02 Clock Pulses 01 = Count Positive CNT Transitions 10 = Count Timer A Underflow Pulses 11 = Count Timer A Underflows While CNT Positive 4-0 Same as CIA Control Reg. A - for Timer B DEOO-DEFF 56832-57087 Reserved for Future I/O Expansion DFOO-DFFF 57088-57343 Reserved for Future I/O Expansion DMA $DF00 8726 DMA Controller for C128 (512K REU) Note: The 8726 DMA controller for C128 is different from the C64 ones in registers 00,01,09 and 0a. DF00 DMA ST STATUS 7 Interrupt Pending (1 = Int. waiting) 6 End of Block (1 = Transfer complete) 5 Fault (1 = Block verify error) 4 Size (0 = 128K, 1 = 512K Exp. Memory) 3-0 Version DF01 DMA CMD COMMAND 7 Exec 6 Reserved (normally 0) 5 Load (1 = Enable auto load) 4 $FF00 (1 = Disable $FF00 decades) 3-2 Reserved (normally 0) 1-0 Mode 00 = Transfer from internal to external 01 = From ext to int 10 = Swap 11 = Verify DF02 DMA ADL HOST ADDRESS LOW DF03 DMA ADH HOST ADDRESS HIGH DF04 DMA LO EXPANSION ADDRESS LOW DF05 DMA HI EXPANSION ADDRESS HIGH DF06 DMA BNK EXPANSION BANK (bits 2-0 only) 7-3 Unused 2-0 Expansion Bank number DF07 DMA DAL TRANSFER LENGTH LOW DF08 DMA DAH TRANSFER LENGTH HIGH DF09 DMA SUM INTERRUPT MASK REGISTER 7 Interrupt Enable (1 = Interrupts enabled) 6 End of Block mask (1 = Interrupt on end of block) 5 Verify Error (1 = Interrupt on verify error) 4-0 Unused (normally all set) DF0A DMA VER VERSION, MAXIMUM MEMORY 7-6 Address Control 00 = Increment both addresses (default) 01 = Fix expansion address 10 = Fix C128 address 11 = Fix both addresses 5-0 Unused (normally all set)
Marko Mäkelä (Marko.Makela@HUT.FI)